CESYS EFM-01 Art no.: C1050-4107

SPARTAN 3E FPGA miniature-module with USB 2.0 interface

139,37 €
This item is not on stock and has to be re-ordered. Available on 2017-02-01
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The EFM-01 embedded FPGA module is based on the Xilinx Spartan-3E® FPGA. This logic-optimized FPGA family is ideal for applications where logic densities matter more than I/O count. In combination with the powerful Cypress FXLPTM USB 2.0 controller, this FPGA is well suited fot embedded control applications, logic integration and DSP co-processing.

Technical Data

FPGA device: XC3S500E-4CPG132C
Number of  I/O signals    50
Interface USB 2.0 (FX2LP)
Size 44mm x 28mm



Despite its small size of only 44 mm x 28 mm, this Spartan-3E™ FPGA module does not come with special fine-pitch connectors. It has standard 0,1" strip headers and is therefore ideal suitable for functional models and prototypes with  breadboards. For use in standard units it can be either plugged or soldered directly.

The FPGA of the EFM-01 module can be configured via the USB 2.0  (FX2LP) interface. The configuration data does not need to travel through the flash memory first. Configuration software is part of the UDK (Universal Development Kit) and comes as executable and source code.

Because it has on-board flash memory, the module is also usable without a USB connection. The configuration flash can be programmed via USB, via JTAG using a Xilinx™ download cable (not included) or by an external processor via the I/O pins in conjunction with an included FPGA design.

An operating voltage of 5 volts DC is required. It can be supplied either via USB (bus powered) or via module pins (self-powered). The EFM01 provides at one of its pins 3.3V.

The included framework CESYS UDK (Universal Development Kit) allows to configure the FPGA via the USB port. Real-world measured data rate of more than 40 Mb/S can be archieved with the UDK3 API and high speed USB 2.0 connections.

The UDK includes drivers for Windows™ XP/Vista/7/8 and Linux™,  APIs for .NET, C++ and C, examples of Labview and Python, the source code of a sample application, an example design in VHDL and the test and analysis tool CESYS UDKLab.


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